Analog-to-digital converter and analog-to-digital conversion method

ABSTRACT

According to an embodiment, an analog-to-digital converter includes a first AD (analog-to-digital) conversion circuit and a second AD conversion circuit. The first AD conversion circuit performs AD conversion of a first input signal to generate an upper-bit digital signal. The second AD conversion circuit performs AD conversion of a sampled signal to generate a lower-bit digital signal. The sampled signal is obtained by sampling a residual signal corresponding to a residue of the AD conversion in the first AD conversion circuit. A period during which the second AD conversion circuit performs AD conversion of the sampled signal overlaps a period during which a second input signal subsequent to the first input signal is settled.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2013-241053, filed Nov. 21, 2013, theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to an analog-to-digitalconverter.

BACKGROUND

In order to implement high-resolution analog-to-digital conversion with,for example, an effective resolution exceeding 14 bits, a multisamplingADC (Analog-to-Digital Converter) such as a ΔΣ modulator is used. Ageneral ADC performs sampling once for one input signal. In contrast, amultisampling ADC performs sampling a plurality of times for one inputsignal and averages the analog-to-digital conversion results in adigital domain. Therefore, the multisampling ADC can achieve a highresolution in analog-to-digital conversion.

The number of times of sampling required for multisampling ADC, however,exponentially increases with respect to the resolution of themultisampling ADC. For example, in order to implement an effectiveresolution of 14 bits by singly using a ΔΣ modulator incorporating a1-bit quantizer, it is necessary to perform sampling 1,000 times and 88times in a primary modulator and a secondary modulator, respectively. Anincrease in the resolution of the multisampling ADC will lead to adecrease in the operating speed of the multisampling ADC.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram exemplifying an ADC according to the firstembodiment;

FIG. 2 is a timing chart exemplifying the operation of the ADC in FIG.1;

FIG. 3 is a block diagram exemplifying an ADC according to the secondembodiment;

FIG. 4 is a timing chart exemplifying the operation of a firstanalog-to-digital conversion circuit in FIG. 3;

FIG. 5 is a block diagram exemplifying an ADC according to the thirdembodiment;

FIG. 6 is a block diagram exemplifying an ADC according to the fourthembodiment;

FIG. 7 is a timing chart exemplifying the operation of the ADC in FIG.6;

FIG. 8 is a block diagram exemplifying an ADC according to the fifthembodiment;

FIG. 9 is a block diagram exemplifying an ADC according to the sixthembodiment;

FIG. 10 is a timing chart exemplifying the operation of a firstanalog-to-digital conversion circuit in FIG. 9;

FIG. 11 is a timing chart exemplifying the operation of the ADC in FIG.9;

FIG. 12 is a block diagram exemplifying an ADC according to the seventhembodiment;

FIG. 13 is a block diagram exemplifying an ADC according to the eighthembodiment;

FIG. 14 is a timing chart exemplifying the operation of the ADC in FIG.13;

FIG. 15 is a block diagram exemplifying an ADC according to the ninthembodiment;

FIG. 16 is a block diagram exemplifying a cyclic ADC; and

FIG. 17 is a block diagram for explaining the operation of the cyclicADC.

DETAILED DESCRIPTION

Embodiments will be described below with reference to the accompanyingdrawings.

According to an embodiment, an analog-to-digital converter includes afirst analog-to-digital conversion circuit and a secondanalog-to-digital conversion circuit. The first analog-to-digitalconversion circuit performs analog-to-digital conversion of a firstinput signal to generate an upper-bit digital signal. The secondanalog-to-digital conversion circuit performs analog-to-digitalconversion of a sampled signal to generate a lower-bit digital signal.The sampled signal is obtained by sampling a residual signalcorresponding to a residue of the analog-to-digital conversion in thefirst analog-to-digital conversion circuit. A period during which thesecond analog-to-digital conversion circuit performs theanalog-to-digital conversion of the sampled signal overlaps a periodduring which a second input signal subsequent to the first input signalis settled.

Note that the same or similar reference numerals denote elements thatare the same as or similar to those described above, and a repetitivedescription of them will be basically omitted.

First Embodiment

As exemplified by FIG. 1, an ADC according to the first embodimentincludes a first analog-to-digital conversion circuit 110, a sampler120, and a second analog-to-digital conversion circuit 130. The ADC inFIG. 1 generates a digital signal 14 including an upper-bit digitalsignal 11 and a lower-bit digital signal 13 by performinganalog-to-digital conversion of an analog signal 10.

The first analog-to-digital conversion circuit 110 corresponds to amultisampling ADC. The first analog-to-digital conversion circuit 110receives the analog signal 10 after the settling of the analog signal10. The first analog-to-digital conversion circuit 110 generates theupper-bit digital signal 11 by performing analog-to-digital conversionof the analog signal 10. The first analog-to-digital conversion circuit110 outputs the upper-bit digital signal 11 to a multiplexer (MUX) (notshown). The first analog-to-digital conversion circuit 110 furtheroutputs a residual signal 12 corresponding to a residue of theanalog-to-digital conversion in the first analog-to-digital conversioncircuit 110 to the sampler 120.

The sampler 120 receives the residual signal 12 from the firstanalog-to-digital conversion circuit 110. The sampler 120 obtains asampled signal by sampling the residual signal 12. The sampler 120 maybe, for example, a sample and hold circuit. The sampler 120 outputs thesampled signal to a second analog-to-digital conversion circuit 130.

The second analog-to-digital conversion circuit 130 corresponds to anADC (e.g., a Nyquist ADC) of a type different from that of amultisampling ADC. The Nyquist ADC can perform analog-to-digitalconversion with a sampling count smaller than that for the multisamplingADC. For example, a cyclic ADC as a kind of Nyquist ADC can performanalog-to-digital conversion with a resolution of N bits in N cycles.The second analog-to-digital conversion circuit 130 receives a sampledsignal from the sampler 120. The second analog-to-digital conversioncircuit 130 generates the lower-bit digital signal 13 by performinganalog-to-digital conversion of the sampled signal. The secondanalog-to-digital conversion circuit 130 outputs the lower-bit digitalsignal 13 to, for example, a multiplexer (not shown).

For example, the multiplexer (not shown) multiplexes the upper-bitdigital signal 11 and the lower-bit digital signal 13, and outputs theresultant signal as the digital signal 14.

In this case, the ADC in FIG. 1 can start settling an analog signalsubsequent to the current analog signal 10 after sampling of theresidual signal 12. That is, this ADC can concurrently execute (i.e.,via pipeline processing) analog-to-digital conversion by the secondanalog-to-digital conversion circuit 130 and the settling of an analogsignal subsequent to the current analog signal 10 (and succeedinganalog-to-digital conversion by the first analog-to-digital conversioncircuit 110).

More specifically, as exemplified by FIG. 2, the operation of the ADC inFIG. 1 corresponds to a repetition of a series of processes includingwaiting for the settling of the analog signal 10 (V_(PIX)),analog-to-digital conversion of the analog signal 10 by the firstanalog-to-digital conversion circuit 110, sampling of the residualsignal 12 by the sampler 120, and analog-to-digital conversion of asampled signal by the second analog-to-digital conversion circuit 130.Since sampling by the sampler 120 is inserted between analog-to-digitalconversion by the first analog-to-digital conversion circuit 110 andanalog-to-digital conversion by the second analog-to-digital conversioncircuit 130, this ADC can start settling the subsequent analog signalwithout waiting for the completion of analog-to-digital conversion bythe second analog-to-digital conversion circuit 130. Therefore, this ADCcan substantially shorten the time required for analog-to-digitalconversion of each analog signal by an overlapping period of the twoprocesses by concurrently executing analog-to-digital conversion by thesecond analog-to-digital conversion circuit 130 and settling of ananalog signal subsequent to the current analog signal 10 (and succeedinganalog-to-digital conversion by the first analog-to-digital conversioncircuit 110). That is, the ADC can perform high-resolutionanalog-to-digital conversion at high speed.

As described above, the ADC according to the first embodiment includes,between the first analog-to-digital conversion circuit for upper bitsand the second analog-to-digital conversion circuit for lower bits, thesampler which samples a residual signal corresponding to a residue ofthe analog-to-digital conversion in the first analog-to-digitalconversion circuit. This ADC can concurrently execute analog-to-digitalconversion by the second analog-to-digital conversion circuit andsettling of the subsequent analog signal (and succeedinganalog-to-digital conversion by the first analog-to-digital conversioncircuit). This ADC can therefore perform high-resolutionanalog-to-digital conversion at high speed.

Second Embodiment

As exemplified by FIG. 3, an ADC according to the second embodimentincludes a first analog-to-digital conversion circuit 210, a sampler120, and a second analog-to-digital conversion circuit 130. The ADC inFIG. 3 generates a digital signal 14 (D_(out)) including an upper-bitdigital signal 11 and a lower-bit digital signal 13 by performinganalog-to-digital conversion of an analog signal 10 (V_(in)).

The sampler 120 in FIG. 3 differs from the sampler 120 in FIG. 1 in thatit receives a residual signal 12 from the first analog-to-digitalconversion circuit 210 instead of the first analog-to-digital conversioncircuit 110.

The first analog-to-digital conversion circuit 210 corresponds to anincremental ΔΣ modulator. The first analog-to-digital conversion circuit210 receives the analog signal 10 after the settling of the analogsignal 10. The first analog-to-digital conversion circuit 210 generatesthe upper-bit digital signal 11 by performing analog-to-digitalconversion of the analog signal 10. The first analog-to-digitalconversion circuit 210 outputs the upper-bit digital signal 11 to amultiplexer. In addition, the first analog-to-digital conversion circuit210 outputs the residual signal 12 corresponding to a residue of theanalog-to-digital conversion in the first analog-to-digital conversioncircuit 210 to the sampler 120.

More specifically, the first analog-to-digital conversion circuit 210includes a subtractor 211, an analog integrator 212, an ADC 213, adigital integrator 214, and a digital-to-analog converter (DAC) 215.

The subtractor 211 receives the analog signal 10, and a feedback signalfrom the DAC 215. The subtractor 211 generates a difference signal bysubtracting the feedback signal from the analog signal 10. Thesubtractor 211 outputs the difference signal to the analog integrator212.

The analog integrator 212 receives the difference signal from thesubtractor 211. The analog integrator 212 generates an integral signalby integrating the difference signal. The analog integrator 212 outputsthe integral signal to the ADC 213. In addition, the analog integrator212 outputs the residual signal 12 as an integral signal to the sampler120 upon completion of analog-to-digital conversion by the firstanalog-to-digital conversion circuit 210. Note that the analogintegrator 212 has a reset function, and resets the integral signal atthe start of analog-to-digital conversion by the first analog-to-digitalconversion circuit 210.

The ADC 213 receives the integral signal from the analog integrator 212.The ADC 213 generates a digital signal by performing analog-to-digitalconversion of the integral signal. The ADC 213 outputs the digitalsignal to the digital integrator 214 and the DAC 215. Note that the ADC213 may be referred to as the internal ADC 213 to be discriminated fromthe ADC in FIG. 3.

The digital integrator 214 receives the digital signal from the ADC 213.The digital integrator 214 generates an integral signal by integratingthe digital signal. The digital integrator 214 outputs the integralsignal as an upper-bit digital signal 11 to the multiplexer uponcompletion of analog-to-digital conversion by the firstanalog-to-digital conversion circuit 210. Note that the digitalintegrator 214 has a reset function, which resets the integral signal atthe start of analog-to-digital conversion by the first analog-to-digitalconversion circuit 210.

The DAC 215 receives a digital signal from the ADC 213. The DAC 215generates a feedback signal of the subsequent cycle by performingdigital-to-analog conversion of the digital signal. The DAC 215 outputsthe feedback signal to the subtractor 211.

The first analog-to-digital conversion circuit 210 operates asexemplified by FIG. 4. In the case of FIG. 4, the analog signal 10 issampled M times (M is an integer equal to or more than 2). Referring toFIG. 4, the ADC 213 generates digital signals D₁, . . . , D_(M) throughthe first to Mth samplings. The integration result (i.e., the total sum)of the digital signals D₁, . . . , D_(M) is output as the upper-bitdigital signal 11. Referring to FIG. 4, the polygonal line represents achange in the voltage of an integral signal held by the analogintegrator 212. The ADC 213 and the DAC 215 use a reference voltageV_(ref). The residual signal 12 has a voltage V_(res).

As shown in FIG. 4, if a digital signal is “1” (in other words, anintegral signal exceeds V_(ref)), since the voltage V_(ref) of afeedback signal corresponding to the digital signal is higher than thatof the analog signal 10, a difference signal having a negative voltageis generated based on the feedback signal. That is, the voltage of theintegral signal held by the analog integrator 212 decreases. Accordingto this feedback control, it is possible to make the voltage of an inputsignal in the ADC 213 fall within a predetermined range.

According to the case of FIG. 4, the following equation holds betweenthe analog signal 10 (V_(in)), the sampling count M, the referencevoltage V_(ref), the digital signals D₁, . . . , D_(M), and the residualsignal V_(res).

${MV}_{in} = {{V_{ref}{\sum\limits_{i = 1}^{M}\; D_{i}}} + V_{res}}$

As described above, the ADC according to the second embodiment uses anincremental ΔΣ modulator as the first analog-to-digital conversioncircuit described in the first embodiment. Therefore, this ADC canobtain effects that are the same as or similar to those of the firstembodiment.

Third Embodiment

As exemplified by FIG. 5, an ADC according to the third embodimentincludes a first analog-to-digital conversion circuit 210, a sampler120, a second analog-to-digital conversion circuit 130, and an amplifier340. The ADC in FIG. 5 generates a digital signal 14 including anupper-bit digital signal 11 and a lower-bit digital signal 13 byperforming analog-to-digital conversion of an analog signal 10 (V_(in)).

The first analog-to-digital conversion circuit 210 in FIG. 5 differsfrom the first analog-to-digital conversion circuit 210 in FIG. 3 inthat it outputs a residual signal 12 to the multiplexer 340 instead ofthe sampler 120. Note that an ADC 213 may be referred to as an internalADC 213 to be discriminated from the ADC in FIG. 5. The sampler 120 inFIG. 5 differs from the sampler 120 in FIG. 3 in that it receives theresidual signal amplified by the amplifier 340 instead of the residualsignal 12 from the second analog-to-digital conversion circuit 130.

The amplifier 340 receives the residual signal 12 from the firstanalog-to-digital conversion circuit 210. The amplifier 340 generates anamplified residual signal by amplifying the residual signal 12 A_(amp)(>1) times. The amplifier 340 outputs the amplified residual signal tothe sampler 120.

In this case, amplifying the residual signal 12 A_(amp) times reducesthe influence of noise generated in the second analog-to-digitalconversion circuit 130 to 1/A_(amp) times as input referred noise. Thatis, the accuracy requirement on the second analog-to-digital conversioncircuit 130 is alleviated as compared with a case in which the aboveamplification is not performed.

As described above, the ADC according to the third embodiment includesthe amplifier between the first analog-to-digital conversion circuit andthe sampler described in the first or second embodiment. Therefore,according to this ADC, the accuracy requirement on the secondanalog-to-digital conversion circuit is alleviated, and hence it ispossible to simplify the second analog-to-digital conversion circuit.

Fourth Embodiment

As exemplified by FIG. 6, an ADC according to the fourth embodimentincludes a first analog-to-digital conversion circuit 410 and a secondanalog-to-digital conversion circuit 130. The ADC in FIG. 6 generates adigital signal 14 (D_(out)) including an upper-bit digital signal 11 anda lower-bit digital signal 13 by performing analog-to-digital conversionof an analog signal 10 (V_(in)).

The second analog-to-digital conversion circuit 130 in FIG. 6 differsfrom the second analog-to-digital conversion circuit 130 in FIG. 3 inthat it receives a sampled signal from the first analog-to-digitalconversion circuit 410 instead of the sampler 120.

The first analog-to-digital conversion circuit 410 corresponds to anincremental ΔΣ modulator. The first analog-to-digital conversion circuit410 can also function as a sampler. The first analog-to-digitalconversion circuit 410 receives the analog signal 10 after the settlingof the analog signal 10. The first analog-to-digital conversion circuit410 generates the upper-bit digital signal 11 by performinganalog-to-digital conversion of the analog signal 10. The firstanalog-to-digital conversion circuit 410 outputs the upper-bit digitalsignal 11 to the multiplexer. In addition, the first analog-to-digitalconversion circuit 410 obtains a sampled signal by sampling a residualsignal corresponding to a residue of the analog-to-digital conversion inthe first analog-to-digital conversion circuit 410. The firstanalog-to-digital conversion circuit 410 then outputs the sampled signalto the second analog-to-digital conversion circuit 130.

More specifically, the first analog-to-digital conversion circuit 410includes a subtractor 211, an analog integrator 212, an ADC 213, adigital integrator 214, a DAC 215, and a switch 416 (SW₁). The firstanalog-to-digital conversion circuit 410 differs from the firstanalog-to-digital conversion circuit 210 in FIG. 3 in that the switch416 is inserted between the subtractor 211 and the analog integrator212. That is, while the switch 416 is on, the first analog-to-digitalconversion circuit 410 is almost equivalent to the firstanalog-to-digital conversion circuit 210 in FIG. 3. Note that an ADC 213may be referred to as an internal ADC 213 to be discriminated from theADC in FIG. 6.

The switch 416 is on over the period during which the firstanalog-to-digital conversion circuit 410 performs the analog-to-digitalconversion of the analog signal 10. On the other hand, the switch 416 isturned off when the first analog-to-digital conversion circuit 410completes analog-to-digital conversion of the analog signal 10. When theswitch 416 is turned off, since the input terminal of the analogintegrator 212 is opened, an integral signal at this time is held. Thatis, when the switch 416 is turned off upon completion ofanalog-to-digital conversion by the first analog-to-digital conversioncircuit 410, the analog integrator 212 holds a residual signal as anintegral signal at this time. The second analog-to-digital conversioncircuit 130 can then generate the lower-bit digital signal 13 byperforming analog-to-digital conversion of the residual signal as theabove sampled signal held by the analog integrator 212.

The first analog-to-digital conversion circuit 410 operates asexemplified by FIG. 7. In the case of FIG. 7, the analog signal 10 issampled M times (M is an integer equal to or more than 2), and thesampled signal is sampled N times (N is an integer). Referring to FIG.7, the ADC 213 generates digital signals D₁ (1), . . . , D_(c)(M)through the first to Mth samplings. The integration result (i.e., thetotal sum) of the digital signals D₁, . . . , D_(M) is output as theupper-bit digital signal 11. Referring to FIG. 7, the secondanalog-to-digital conversion circuit 130 generates digital signalsD_(F)(1), . . . , D_(F)(N) through the first to Nth samplings. Inaddition, FIG. 7 shows a change in the state of the switch 416.Referring to FIG. 7, the polygonal line represents a change in thevoltage of an integral signal held by the analog integrator 212. The ADC213 and the DAC 215 use a reference voltage V_(ref). The residual signal12 has a voltage V_(res).

As shown in FIG. 7, the switch 416 is on over an operation period of thefirst analog-to-digital conversion circuit 410, and is off over theoperation period of the second analog-to-digital conversion circuit 130.The first analog-to-digital conversion circuit 410 functions as anincremental ΔΣ modulator over the period during which the switch 416 ison. The first analog-to-digital conversion circuit 410 (to be precise,the analog integrator 212) functions as a sampler over the period duringwhich the switch 416 is off.

As described above, the ADC according to the fourth embodiment includesthe first analog-to-digital conversion circuit for upper bits and thesecond analog-to-digital conversion circuit for lower bits. This firstanalog-to-digital conversion circuit time-divisionally functions as anincremental ΔΣ modulator and a sampler. Therefore, the operation thisADC can perform is the same as or similar to that of the ADC accordingto the second embodiment described above without requiring any dedicatedsampler. That is, according to this ADC, it is possible to simplify thearrangement while maintaining the effects that are the same as orsimilar to those of the second embodiment described above.

Fifth Embodiment

As exemplified by FIG. 8, the ADC according to the fifth embodimentincludes a first analog-to-digital conversion circuit 410, a secondanalog-to-digital conversion circuit 130, and an amplifier 340. The ADCin FIG. 8 generates a digital signal 14 including an upper-bit digitalsignal 11 and a lower-bit digital signal 13 by performinganalog-to-digital conversion of an analog signal 10 (V_(in)).

The first analog-to-digital conversion circuit 410 in FIG. 8 differsfrom the first analog-to-digital conversion circuit 410 in FIG. 6 inthat it outputs a sampled signal to the amplifier 340 instead of thesecond analog-to-digital conversion circuit 130. The secondanalog-to-digital conversion circuit 130 in FIG. 8 differs from thesecond analog-to-digital conversion circuit 130 in FIG. 6 in that itreceives the sampled signal amplified by the amplifier 340 instead of asampled signal from the first analog-to-digital conversion circuit 410.Note that an ADC 213 may be referred to as an internal ADC 213 to bediscriminated from the ADC in FIG. 8.

The amplifier 340 receives a sampled signal from the firstanalog-to-digital conversion circuit 410. The amplifier 340 generates anamplified sampled signal by amplifying the sampled signal A_(amp) times.The amplifier 340 outputs the amplified sampled signal to the secondanalog-to-digital conversion circuit 130.

In this case, amplifying the sampled signal A_(amp) times reduces theinfluence of noise generated in the second analog-to-digital conversioncircuit 130 to 1/A_(amp) times as input referred noise. That is, theaccuracy requirement on the second analog-to-digital conversion circuit130 is alleviated as compared with a case in which the aboveamplification is not performed.

As described above, the ADC according to the fifth embodiment includesthe amplifier between the first analog-to-digital conversion circuit andthe second analog-to-digital conversion circuit described in the fourthembodiment. Therefore, according to this ADC, the accuracy requirementon the second analog-to-digital conversion circuit is alleviated, andhence it is possible to simplify the second analog-to-digital conversioncircuit.

Sixth Embodiment

An ADC according to the sixth embodiment can be applied to, for example,a CMOS (Complementary Metal Oxide Semiconductor) image sensor. An ADCfor a CMOS image sensor needs to perform analog-to-digital conversion ofthe difference signal between two analog signals called a reset signaland a set signal to generate one pixel value data. That is, in thisembodiment, an input analog signal corresponds to the difference signalbetween the first analog signal called a reset signal and the secondanalog signal called a set signal.

As exemplified by FIG. 9, the ADC according to the sixth embodimentincludes a first analog-to-digital conversion circuit 510 and a secondanalog-to-digital conversion circuit 130. The ADC in FIG. 9 generates adigital signal 14 (D_(out)) including an upper-bit digital signal 11 anda lower-bit digital signal 13 by performing analog-to-digital conversionof an analog signal 10 (V_(in)).

The first analog-to-digital conversion circuit 510 corresponds to anincremental ΔΣ modulator. Like the first analog-to-digital conversioncircuit 410 in FIG. 6, the first analog-to-digital conversion circuit510 can also function as a sampler. The first analog-to-digitalconversion circuit 510 receives the first analog signal after thesettling of the first analog signal (which will also be referred to as areset signal V_(R)). The first analog-to-digital conversion circuit 510performs analog-to-digital conversion of the first analog signal.Thereafter, the first analog-to-digital conversion circuit 510 receivesthe second analog signal after the settling of the second analog signal(which will also be referred to as a set signal V_(S)). The firstanalog-to-digital conversion circuit 510 performs analog-to-digitalconversion of the second analog signal. The first analog-to-digitalconversion circuit 510 generates the upper-bit digital signal 11corresponding to the analog-to-digital conversion result of thedifference signal between the first and second analog signals bycomputing the analog-to-digital conversion results of the first andsecond analog signals. The first analog-to-digital conversion circuit510 outputs the upper-bit digital signal 11 to a multiplexer. Inaddition, the first analog-to-digital conversion circuit 510 obtains asampled signal by sampling a residual signal corresponding to a residueof the analog-to-digital conversion in the first analog-to-digitalconversion circuit 510. The first analog-to-digital conversion circuit510 then outputs the sampled signal to the second analog-to-digitalconversion circuit 130.

More specifically, the first analog-to-digital conversion circuit 510includes a subtractor 211, an analog integrator 212, an ADC 213, adigital integrator 214, a DAC 215, a switch 416 (SW₁), a sign selector517, and a multiplier 518.

The subtractor 211 in FIG. 9 differs from the subtractor 211 in FIG. 6in that it outputs a difference signal to the multiplier 518 instead ofthe analog integrator 212. The analog integrator 212 in FIG. 9 differsfrom the analog integrator 212 in FIG. 6 in that it receives a productsignal from the multiplier 518 via the switch 416 instead of adifference signal from the subtractor 211. Note that the ADC 213 may bereferred to as the internal ADC 213 to be discriminated from the ADC inFIG. 9.

The sign selector 517 selects signs corresponding to the polarities ofthe first and second analog signals. More specifically, the signselector 517 selects a positive sign (+1) for the first analog signal asthe reset signal V_(R). On the other hand, the sign selector 517 selectsa negative sign (−1) for the second analog signal as the set signalV_(S). The sign selector 517 outputs the selected signs to themultiplier 518.

The multiplier 518 receives a difference signal from the subtractor 211,and signs from the sign selector 517. The multiplier 518 generates aproduct signal by multiplying the difference signal by the signs. Morespecifically, the multiplier 518 multiplies the first difference signalbased on a reset signal V_(R) by the positive sign (+1), and the seconddifference signal based on a set signal V_(S) by the sign (−1). In otherwords, the multiplier 518 maintains the sign of the first differencesignal based on the reset signal V_(R), and inverts the sign of thesecond difference signal based on the set signal V_(S). The multiplier518 outputs the product signal to the analog integrator 212 via theswitch 416.

The first analog-to-digital conversion circuit 510 operates asexemplified by FIG. 10. In the case of FIG. 10, the reset signal V_(R)and the set signal V_(S) each are sampled M times (M is an integer equalto or more than 2).

Referring to FIG. 10, the ADC 213 generates digital signals D_(R)(1), .. . , D_(R)(M) through the first to Mth samplings of the reset signalV_(R). The ADC 213 generates digital signals D_(S)(1), . . . , D_(S)(M)through the first to Mth samplings of the set signal V_(S). Theintegration results (i.e., the total sums) of the digital signals D_(R)(1), . . . , D_(R) and D_(S)(1), . . . , D_(S) are output as theupper-bit digital signals 11. Referring to FIG. 10, the polygonal linerepresents a change in the voltage of an integral signal held by theanalog integrator 212. The ADC 213 and the DAC 215 use referencevoltages V_(refP) and V_(refN). The residual signal 12 has a voltageV_(res).

As shown in FIG. 10, in a sampling period of the reset signal V_(R),when the digital signal is “1” (in other words, the integral signalexceeds V_(refP)), since the voltage V_(refP) of a feedback signalcorresponding to the digital signal is higher than the voltage of thefirst analog signal, a product signal having a negative voltage isgenerated based on the feedback signal. That is, the voltage of theintegral signal held by the analog integrator 212 decreases. Accordingto this feedback control, it is possible to make the voltages of inputsignals in the ADC 213 fall within a predetermined range. Likewise, asshown in FIG. 10, in a sampling period of the set signal V_(S), when thedigital signal is “−1” (in other words, the integral signal becomeslower than V_(refN)), since the voltage V_(refN) of a feedback signalcorresponding to the digital signal is higher than the voltage of thesecond analog signal, a product signal having a positive voltage isgenerated based on the feedback signal. That is, the voltage of theintegral signal held by the analog integrator 212 increases. Accordingto this feedback control, it is possible to make the voltages of inputsignals in the ADC 213 fall within a predetermined range.

According to the case of FIG. 10, the following equation holds betweenthe first analog signal V_(R), the second analog signal V_(S), thesampling count M, the reference voltages V_(refP) and V_(refN), thedigital signals D_(R)(1), . . . , D_(R)(M) and D_(S)(1), . . . ,D_(S)(M), and the residual signal V_(res).

${{MV}_{R} - {MV}_{S}} = {{V_{refP}{\sum\limits_{i = 1}^{M}\;{D_{R}(i)}}} + {V_{refN}{\sum\limits_{i = 1}^{M}\;{D_{S}(i)}}} + V_{res}}$

As exemplified by FIG. 11, the operation of the ADC in FIG. 9corresponds to a repetition of a series of processes includinganalog-to-digital conversion of the first analog signal V_(R) by thefirst analog-to-digital conversion circuit 510, analog-to-digitalconversion of the second analog signal V_(S) by the firstanalog-to-digital conversion circuit 510, and analog-to-digitalconversion of a residual signal by the second analog-to-digitalconversion circuit 130. Although not shown, the sampling of a residualsignal by the first analog-to-digital conversion circuit 510 is insertedbetween analog-to-digital conversion of the second analog signal V_(S)by the first analog-to-digital conversion circuit 510 andanalog-to-digital conversion of a residual signal by the secondanalog-to-digital conversion circuit 130. Therefore, this ADC can startsettling the subsequent analog signal (that is, the subsequent resetsignal and set signal) without waiting for the completion ofanalog-to-digital conversion by the second analog-to-digital conversioncircuit 130. Therefore, this ADC can shorten the time required foranalog-to-digital conversion of each analog signal by an overlappingperiod of the two processes by concurrently executing analog-to-digitalconversion by the second analog-to-digital conversion circuit 130 andsettling of an analog signal subsequent to the analog signal 10 (andsucceeding analog-to-digital conversion by the first analog-to-digitalconversion circuit 510). That is, the ADC can perform high-resolutionanalog-to-digital conversion at high speed.

In addition, since the first analog-to-digital conversion circuit 510 inFIG. 9 performs analog-to-digital conversion of each of a reset signaland a set signal, it is possible to assign a long time foranalog-to-digital conversion by the second analog-to-digital conversioncircuit 130. More specifically, the magnitude of the time required foranalog-to-digital conversion by the second analog-to-digital conversioncircuit 130 does not influence the operating speed of the ADC in FIG. 9unless the time required for analog-to-digital conversion by the secondanalog-to-digital conversion circuit 130 exceeds the sum of the timesrequired for the settling of a reset signal, analog-to-digitalconversion of the reset signal by the first analog-to-digital conversioncircuit 510, the settling of a set signal, analog-to-digital conversionof the set signal by the first analog-to-digital conversion circuit 510,and the sampling of a residual signal.

As described above, the ADC according to the sixth embodiment includesthe first analog-to-digital conversion circuit for upper bits and thesecond analog-to-digital conversion circuit for lower bits. This ADCconcurrently executes analog-to-digital conversion by the secondanalog-to-digital conversion circuit and settling of the subsequentanalog signal (and succeeding analog-to-digital conversion by the firstanalog-to-digital conversion circuit). This ADC can therefore performhigh-resolution analog-to-digital conversion at high speed. In addition,according to the ADC, it is possible to assign a long time toanalog-to-digital conversion by the second analog-to-digital conversioncircuit because the second analog-to-digital conversion circuitconcurrently executes analog-to-digital conversion of the residualsignal with analog-to-digital conversion of two analog signals called areset signal and a set signal. That is, the operating speed required forthe second analog-to-digital conversion circuit can be reduced.

Seventh Embodiment

As exemplified by FIG. 12, an ADC according to the seventh embodimentincludes a first analog-to-digital conversion circuit 610, a sampler120, and a second analog-to-digital conversion circuit 130. The ADC inFIG. 12 generates a digital signal 14 (D_(out)) including an upper-bitdigital signal 11 and a lower-bit digital signal 13 by performinganalog-to-digital conversion of an analog signal 10 (V_(in)).

The sampler 120 in FIG. 12 differs from the sampler 120 in FIG. 3 inthat it receives the residual signal 12 from the first analog-to-digitalconversion circuit 610 instead of the first analog-to-digital conversioncircuit 210.

The first analog-to-digital conversion circuit 610 corresponds to anerror feedback ΔΣ modulator. The first analog-to-digital conversioncircuit 610 receives the analog signal 10 after the settling of theanalog signal 10. The first analog-to-digital conversion circuit 610generates the upper-bit digital signal 11 by performinganalog-to-digital conversion of the analog signal 10. The firstanalog-to-digital conversion circuit 610 outputs the upper-bit digitalsignal 11 to a multiplexer. In addition, the first analog-to-digitalconversion circuit 610 outputs the residual signal 12 corresponding to aresidue of the analog-to-digital conversion in the firstanalog-to-digital conversion circuit 610 to the sampler 120.

More specifically, the first analog-to-digital conversion circuit 610includes a subtractor 611, an ADC 612, a digital integrator 613, asubtractor 614, and a DAC 615.

The subtractor 611 receives the analog signal 10, and a quantizationerror signal from the subtractor 614. The subtractor 611 generates adifference signal by subtracting a quantization error signal V_(EQ) fromthe analog signal 10. The subtractor 611 outputs the difference signalto the ADC 612 and the subtractor 614.

The ADC 612 receives the difference signal from the subtractor 611. TheADC 612 generates a digital signal by performing analog-to-digitalconversion of the difference signal. The ADC 612 outputs the digitalsignal to the digital integrator 613 and the DAC 615. Note that the ADC612 may be referred to as the internal ADC 612 to be discriminated fromthe ADC in FIG. 12. The following equation holds between the digitalsignal (D), the analog signal 10 (V_(in)), and the quantization errorsignal V_(EQ).D=V _(in)+(1−z ⁻¹)V _(EQ)

The digital integrator 613 receives a digital signal from the ADC 612.The digital integrator 613 generates an integral signal by integratingthe digital signal. The digital integrator 613 outputs the integralsignal as the upper-bit digital signal 11 to the multiplexer uponcompletion of analog-to-digital conversion by the firstanalog-to-digital conversion circuit 610. Note that the digitalintegrator 613 has a reset function, and resets the integral signal atthe start of analog-to-digital conversion by the first analog-to-digitalconversion circuit 610.

The DAC 615 receives a digital signal from the ADC 612. The DAC 615generates an analog signal by performing analog-to-digital conversion ofthe digital signal. The DAC 615 outputs the analog signal to thesubtractor 614.

The subtractor 614 receives the difference signal from the subtractor611, and the analog signal from the DAC 615. The subtractor 614generates a quantization error signal by subtracting the differencesignal from the analog signal. The subtractor 614 outputs thequantization error signal to the subtractor 611. In addition, thesubtractor 614 outputs the quantization error signal as the residualsignal 12 to the sampler 120 upon completion of analog-to-digitalconversion by the first analog-to-digital conversion circuit 610.

As described above, the ADC according to the seventh embodiment uses anerror feedback ΔΣ modulator as the first analog-to-digital conversioncircuit described in the first embodiment. According to this ADC, it ispossible to obtain the same effects as, or effects similar to those ofthe first embodiment.

Eighth Embodiment

As exemplified by FIG. 13, an ADC according to the eighth embodimentincludes a first analog-to-digital conversion circuit 210, a sample andhold circuit 720, a second analog-to-digital conversion circuit 730, andan amplifier 740. The ADC in FIG. 13 generates a digital signal 14(D_(out)) including an upper-bit digital signal 11 and a lower-bitdigital signal 13 by performing analog-to-digital conversion of ananalog signal 10 (V_(in)).

The first analog-to-digital conversion circuit 210 in FIG. 13 differsfrom the first analog-to-digital conversion circuit 210 in FIG. 5 inthat it outputs a residual signal 12 to the amplifier 740 instead of theamplifier 340. Note that an ADC 213 may be referred to as an internalADC 213 to be discriminated from the ADC in FIG. 13.

The amplifier 740 receives the residual signal 12 from the firstanalog-to-digital conversion circuit 210. The amplifier 740 generates anamplified residual signal by amplifying the residual signal 12 M times.The amplifier 740 outputs the amplified residual signal to the sampleand hold circuit 720.

In this case, amplifying the residual signal 12 M (>1) times reduces theinfluence of noise generated in the second analog-to-digital conversioncircuit 730 to 1/M times as input referred noise. That is, the accuracyrequirement on the second analog-to-digital conversion circuit 730 isalleviated as compared with a case in which the above amplification isnot performed.

The sample and hold circuit 720 receives the amplified residual signalfrom the amplifier 740. The sample and hold circuit 720 obtains asampled signal by sampling and holding the amplified residual signal.The sample and hold circuit 720 may be, for example, a sampler of a typedifferent from that of a sample and hold circuit. The sample and holdcircuit 720 outputs the sampled signal to the second analog-to-digitalconversion circuit 730.

The second analog-to-digital conversion circuit 730 corresponds to asingle-slope ADC. The single-slope ADC can be implemented with a smallerarea than that for other types of ADCs. In addition, the single-slopeADC consumes less power than other types of ADCs since it does notrequire an amplifier.

The second analog-to-digital conversion circuit 730 receives a sampledsignal from the sample and hold circuit 720. The secondanalog-to-digital conversion circuit 730 generates the lower-bit digitalsignal 13 by performing analog-to-digital conversion of the sampledsignal. The second analog-to-digital conversion circuit 730 outputs thelower-bit digital signal 13.

More specifically, the second analog-to-digital conversion circuit 730includes a ramp wave generator 731, a comparator 732, and a counter 733.

The ramp wave generator 731 generates a ramp wave V_(ramp) over anoperation period of the second analog-to-digital conversion circuit 730,as shown in FIG. 14. The ramp wave generator 731 outputs the ramp waveto the first input terminal of the comparator 732.

The comparator 732 includes first and second input terminals. Thecomparator 732 receives a ramp wave from the ramp wave generator 731 viathe first input terminal, and a sampled signal from the sample and holdcircuit 720 via the second input terminal. The comparator 732 outputsthe comparison result signal obtained from the ramp wave and the sampledsignal in synchronism with a clock signal (not shown) to the counter733. For example, the comparator 732 may output a comparison resultsignal of “1” if the voltage of the sampled signal is equal to or morethan that of the ramp wave, and a comparison result signal of “0”otherwise.

The counter 733 receives the comparison result signal from thecomparator 732. The counter 733 counts the comparison result signal. Thetime (the number of clocks) taken to invert the comparison result signal(i.e., to raise the voltage of the ramp wave to a voltage higher thanthat of the sampled signal) is proportional to the voltage of thesampled signal. Therefore, the count value of the comparison resultsignal corresponds to the analog-to-digital conversion result of thesampled signal. The counter 733 outputs the count value as the lower-bitdigital signal 13 to the multiplexer.

As described above, the ADC according to the eighth embodiment canimplement a second analog-to-digital conversion circuit for lower bitswith a small area and low power consumption by using a single-slope ADC.In addition, this ADC includes, between the first analog-to-digitalconversion circuit for upper bits and the second analog-to-digitalconversion circuit for lower bits, the sample and hold circuit whichsamples and holds a residual signal corresponding to a residue of theanalog-to-digital conversion in the first analog-to-digital conversioncircuit. The ADC concurrently executes analog-to-digital conversion bythe second analog-to-digital conversion circuit and settling of thesubsequent analog signal (and succeeding analog-to-digital conversion bythe first analog-to-digital conversion circuit). The ADC can thereforeperform high-resolution analog-to-digital conversion at high speed. Inaddition, the ADC includes the amplifier between the firstanalog-to-digital conversion circuit and the sample and hold circuit.Therefore, according to the ADC, the accuracy requirement on the secondanalog-to-digital conversion circuit is alleviated, and hence it ispossible to simplify the second analog-to-digital conversion circuit.

Ninth Embodiment

As exemplified by FIG. 15, an ADC according to the ninth embodimentincludes a first analog-to-digital conversion circuit 210, a sample andhold circuit 820, and a second analog-to-digital conversion circuit 830.The ADC in FIG. 15 generates a digital signal 14 including an upper-bitdigital signal 11 and a lower-bit digital signal 13 by performinganalog-to-digital conversion of an analog signal 10 (V_(in)).

The first analog-to-digital conversion circuit 210 in FIG. 15 differsfrom the first analog-to-digital conversion circuit 210 in FIG. 3 inthat it outputs a residual signal 12 to the sample and hold circuit 820instead of a sampler 120. Note that an ADC 213 may be referred to as aninternal ADC 213 to be discriminated from the ADC in FIG. 15.

The sample and hold circuit 820 receives the residual signal 12 from thefirst analog-to-digital conversion circuit 210. The sample and holdcircuit 820 obtains a sampled signal by sampling and holding theresidual signal 12. The sample and hold circuit 820 may be replaced by asampler of a type different from that of a sample and hold circuit. Thesample and hold circuit 820 outputs the sampled signal to the secondanalog-to-digital conversion circuit 830.

The second analog-to-digital conversion circuit 830 corresponds to acyclic ADC. The cyclic ADC can perform analog-to-digital conversion athigh speed. More specifically, the cyclic ADC performs analog-to-digitalconversion with a resolution of N bits in N cycles. In addition, sincethe cyclic ADC performs analog-to-digital conversion with a resolutionof N bits as exemplified by FIG. 17 by repeatedly operating a unitcircuit exemplified by FIG. 16 over N cycles, even an increase inresolution hardly increases the mounting area.

The second analog-to-digital conversion circuit 830 receives a sampledsignal from the sample and hold circuit 820. The secondanalog-to-digital conversion circuit 830 generates the lower-bit digitalsignal 13 by performing analog-to-digital conversion of the sampledsignal. The second analog-to-digital conversion circuit 830 outputs thelower-bit digital signal 13.

More specifically, the second analog-to-digital conversion circuit 830includes a selector 831, an ADC 832, a DAC 833, a subtractor 834, and anamplifier 835.

The selector 831 includes first and second input terminals. The selector831 receives a sampled signal from the sample and hold circuit 820 viathe first input terminal, and a feedback signal from the amplifier 835via the second input terminal. The selector 831 obtains a selectionsignal by selecting one of these two input signals. More specifically,the selector 831 selects the sampled signal in the first cycle, and thefeedback signal in the second or subsequent cycle. The selector 831outputs the selection signal to the ADC 832. If the secondanalog-to-digital conversion circuit 830 also operates in the subsequentcycle, the selector 831 needs to also output the selection signal to thesubtractor 834.

The ADC 832 receives the selection signal from the selector 831. The ADC832 generates a digital signal by performing analog-to-digitalconversion of the selection signal. The ADC 832 outputs the digitalsignal to the multiplexer. This digital signal corresponds to a 1-bitdigital signal of the lower-bit digital signal 13. If the secondanalog-to-digital conversion circuit 830 also operates in the subsequentcycle, the ADC 832 needs to also output the digital signal to the DAC833. Note that the ADC 832 may be referred to as the internal ADC 832 tobe discriminated from the ADC in FIG. 15.

The DAC 833 receives the digital signal from the ADC 832. The DAC 833generates an analog signal by performing digital-to-analog conversion ofthe digital signal. The DAC 833 outputs the analog signal to thesubtractor 834.

The subtractor 834 receives the selection signal from the selector 831,and the analog signal from the DAC 833. The subtractor 834 generates aresidual signal corresponding to a residue of the analog-to-digitalconversion in the ADC 832 by subtracting the analog signal from theselection signal. The subtractor 834 outputs the residual signal to theamplifier 835.

The amplifier 835 receives the residual signal from the subtractor 834.The amplifier 835 generates a feedback signal by amplifying the residualsignal twice. The amplifier 835 outputs the feedback signal to thesecond input terminal of the selector 831.

That is, the second analog-to-digital conversion circuit 830 generatesan MSB (Most Significant Bit) digital signal of the lower-bit digitalsignal 13 by comparing the voltage of the sampled signal with areference voltage in the first cycle. In addition, the secondanalog-to-digital conversion circuit 830 generates an SSB (SecondSignificant Bit) digital signal of the lower-bit digital signal 13 bycomparing the above reference voltage with the voltage obtained bydoubling the voltage of the residual signal, generated in the firstcycle, in the second cycle. Likewise, in the Nth cycle, the secondanalog-to-digital conversion circuit 830 generates an LSB (LeastSignificant Bit) digital signal of the lower-bit digital signal 13 bycomparing the above reference voltage with the voltage obtained bydoubling the residual signal generated in the (N−1)th cycle.

As described above, the ADC according to the ninth embodiment can makethe second analog-to-digital conversion circuit for lower bits operateat high speed by using a cyclic ADC. This ADC includes, between thefirst analog-to-digital conversion circuit for upper bits and the secondanalog-to-digital conversion circuit for lower bits, the sample and holdcircuit which samples and holds a residual signal corresponding to aresidue of the analog-to-digital conversion in the firstanalog-to-digital conversion circuit. The ADC concurrently executesanalog-to-digital conversion by the second analog-to-digital conversioncircuit and settling of the subsequent analog signal (and succeedinganalog-to-digital conversion by the first analog-to-digital conversioncircuit). The ADC can therefore perform high-resolutionanalog-to-digital conversion at high speed.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel methods and systems describedherein may be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the methods andsystems described herein may be made without departing from the spiritof the inventions. The accompanying claims and their equivalents areintended to cover such forms or modifications as would fall within thescope and spirit of the inventions.

What is claimed is:
 1. An analog-to-digital converter comprising: afirst analog-to-digital conversion circuit which performsanalog-to-digital conversion of a first input signal to generate anupper-bit digital signal; and a second analog-to-digital conversioncircuit which performs analog-to-digital conversion of a sampled signalto generate a lower-bit digital signal, the sampled signal beingobtained by sampling a residual signal corresponding to a residue of theanalog-to-digital conversion in the first analog-to-digital conversioncircuit, wherein a period during which the second analog-to-digitalconversion circuit performs the analog-to-digital conversion of thesampled signal overlaps a period during which a second input signalsubsequent to the first input signal is settled.
 2. The converteraccording to claim 1, further comprising a sampler which samples theresidual signal to obtain the sampled signal.
 3. The converter accordingto claim 1, further comprising: an amplifier which amplifies theresidual signal to generate an amplified residual signal; and a samplerwhich samples the amplified residual signal to obtain the sampledsignal.
 4. The converter according to claim 1, wherein the firstanalog-to-digital conversion circuit comprises: a subtractor whichsubtracts a feedback signal from the first input signal to generate adifference signal; an analog integrator which integrates the differencesignal to generate an integral signal; an internal analog-to-digitalconverter which performs analog-to-digital conversion of the integralsignal to generate a digital signal; a digital integrator whichintegrates the digital signal to generate the upper-bit digital signal;and a digital-to-analog converter which performs digital-to-analogconversion of the digital signal to generate a feedback signal of asubsequent cycle.
 5. The converter according to claim 1, wherein thefirst analog-to-digital conversion circuit comprises: a subtractor whichsubtracts a feedback signal from the first input signal to generate adifference signal; an analog integrator which integrates the differencesignal to generate an integral signal; an internal analog-to-digitalconverter which performs analog-to-digital conversion of the integralsignal to generate a digital signal; a digital integrator whichintegrates the digital signal to generate the upper-bit digital signal;a digital-to-analog converter which performs digital-to-analogconversion of the digital signal to generate a feedback signal of asubsequent cycle; and a switch inserted between the subtractor and theanalog integrator and which is turned on over a period during which thefirst analog-to-digital conversion circuit performs theanalog-to-digital conversion of the first input signal and turned offupon completion of analog-to-digital conversion of the first inputsignal by the first analog-to-digital conversion circuit, and the analogintegrator holds, as the sampled signal, the integral signal at the timewhen the switch is turned off.
 6. The converter according to claim 1,wherein the first input signal corresponds to a difference signalbetween a first analog signal and a second analog signal, and the firstanalog-to-digital conversion circuit comprises: a subtractor whichsubtracts a feedback signal from the first analog signal and the secondanalog signal to respectively generate a first difference signal and asecond difference signal; a multiplier which multiplies the firstdifference signal by a positive sign and multiplies the seconddifference signal by a negative sign to generate a product signal; ananalog integrator which integrates the product signal to generate anintegral signal; an internal analog-to-digital converter which performsanalog-to-digital conversion of the integral signal to generate adigital signal; a digital integrator which integrates the digital signalto generate the upper-bit digital signal; and a digital-to-analogconverter which performs digital-to-analog conversion of the digitalsignal to generate a feedback signal of a subsequent cycle.
 7. Ananalog-to-digital conversion method comprising: performing, by a firstanalog-to-digital conversion circuit, analog-to-digital conversion of afirst input signal to generate an upper-bit digital signal; andperforming, by a second analog-to-digital conversion circuit,analog-to-digital conversion of a sampled signal to generate a lower-bitdigital signal, the sampled signal being obtained by sampling a residualsignal corresponding to a residue of the analog-to-digital conversion inthe first analog-to-digital conversion circuit, wherein a period duringwhich the second analog-to-digital conversion circuit performs theanalog-to-digital conversion of the sampled signal overlaps a periodduring which a second input signal subsequent to the first input signalis settled.